 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MCP6141/2/3/4 600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps Features: * * * * * * * * * Low Quiescent Current: 600 nA/amplifier (typ.) Gain Bandwidth Product: 100 kHz (typ.) Stable for gains of 10 V/V or higher Rail-to-Rail Input/Output Wide Supply Voltage Range: 1.4V to 5.5V Available in Single, Dual, and Quad Chip Select (CS) with MCP6143 Available in 5-lead and 6-lead SOT-23 Packages Temperature Ranges: - Industrial: -40C to +85C - Extended: -40C to +125C Description: The MCP6141/2/3/4 family of non-unity gain stable operational amplifiers (op amps) from Microchip Technology Inc. operate with a single supply voltage as low as 1.4V, while drawing less than 1 A (max.) of quiescent current per amplifier. These devices are also designed to support rail-to-rail input and output operation. This combination of features supports battery-powered and portable applications. The MCP6141/2/3/4 amplifiers have a gain bandwidth product of 100 kHz (typ.) and are stable for gains of 10 V/V or higher. These specifications make these op amps appropriate for battery powered applications where a higher frequency response from the amplifier is required. The MCP6141/2/3/4 family operational amplifiers are offered in single (MCP6141), single with Chip Select (CS) (MCP6143), dual (MCP6142) and quad (MCP6144) configurations. The MCP6141 device is available in the 5-lead SOT-23 package, and the MCP6143 device is available in the 6-lead SOT-23 package. Applications: * * * * Toll Booth Tags Wearable Products Temperature Measurement Battery Powered Available Tools: * SPICE Macro Models (at www.microchip.com) * FilterLabTM Software (at www.microchip.com) Package Types MCP6141 PDIP, SOIC, MSOP NC 1 VIN- 2 VIN+ 3 VSS 4 8 NC 7 VDD 6 VOUT 5 NC MCP6143 PDIP, SOIC, MSOP NC 1 VIN- 2 VIN+ 3 VSS 4 8 CS 7 VDD 6 VOUT 5 NC Related Devices: * MCP6041/2/3/4: Unity Gain Stable Op Amps Typical Application R1 V1 R2 V2 R3 V3 MCP614X VREF Inverting, Summing Amplifier RF VOUT MCP6141 SOT-23-5 VOUT 1 VSS 2 VIN+ 3 4 VIN- 5 VDD MCP6143 SOT-23-6 VOUT 1 VSS 2 VIN+ 3 6 VDD 5 CS 4 VIN- MCP6142 PDIP, SOIC, MSOP VOUTA 1 VINA- 2 VINA+ 3 VSS 4 MCP6144 PDIP, SOIC, TSSOP 14 VOUTD 13 VIND- 12 VIND+ 11 VSS 10 VINC+ 9 VINC- 8 VOUTC 8 VDD VOUTA 1 7 VOUTB VINA- 2 6 VINB- VINA+ 3 5 VINB+ VDD 4 VINB+ 5 VINB- 6 VOUTB 7 (c) 2005 Microchip Technology Inc. DS21668B-page 1 MCP6141/2/3/4 1.0 ELECTRICAL CHARACTERISTICS Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings VDD - VSS ........................................................................7.0V All Inputs and Outputs .................... VSS - 0.3V to VDD + 0.3V Difference Input voltage ...................................... |VDD - VSS| Output Short Circuit Current ..................................continuous Current at Input Pins ....................................................2 mA Current at Output and Supply Pins ............................30 mA Storage Temperature.................................... -65C to +150C Junction Temperature.................................................. +150C ESD protection on all pins (HBM; MM) ................ 4 kV; 200V DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = 25C, VCM = VDD/2, VOUT VDD/2, and RL = 1 M to VDD/2. Parameters Input Offset Input Offset Voltage Drift with Temperature Power Supply Rejection Input Bias Current and Impedance Input Bias Current Industrial Temperature Extended Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode Common Mode Input Range Common Mode Rejection Ratio Sym. VOS VOS/TA PSRR IB IB IB IOS ZCM ZDIFF VCMR CMRR CMRR CMRR Min. -3 -- 70 -- -- -- -- -- -- VSS-0.3 62 60 60 95 Typ. -- 1.5 85 1 20 1200 1 1013||6 1013||6 -- 80 75 80 115 Max. +3 -- -- -- 100 5000 -- -- -- VDD+0.3 -- -- -- -- Units mV Conditions VCM = VSS VCM = VSS, TA = -40C to +125C VCM = VSS V/C dB pA pA pA pA ||pF ||pF V dB dB dB dB TA = +85 TA = +125 VDD = 5V, VCM = -0.3V to 5.3V VDD = 5V, VCM = 2.5V to 5.3V VDD = 5V, VCM = -0.3V to 2.5V RL = 50 k to VDD/2, VOUT = 0.1V to VDD-0.1V RL = 50 k to VDD/2, 0.5V output overdrive RL = 50 k to VDD/2, AOL 95 dB VDD = 1.4V VDD = 5.5V Open Loop Gain DC Open Loop Gain (large signal) Output Maximum Output Voltage Swing Linear Region Output Voltage Swing Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per amplifier VDD IQ 1.4 0.3 -- 0.6 5.5 1.0 V VOL, VOH VOVR ISC ISC VSS + 10 VSS + 100 -- -- -- -- 2 20 VDD - 10 VDD - 100 -- -- mV mV mA mA AOL A IO = 0 DS21668B-page 2 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = 25C, VCM = VDD/2, VOUT VDD/2, RL = 1 M to VDD/2, and CL = 60 pF. Parameters AC Response Gain Bandwidth Product Slew Rate Phase Margin Noise Input Voltage Noise Input Voltage Noise Density Input Current Noise Density Sym. GBWP SR PM Eni eni ini Min. -- -- -- -- -- -- Typ. 100 24 60 5.0 170 0.6 Max. -- -- -- -- -- -- Units kHz V/ms G = +10 Conditions VP-P f = 0.1 Hz to 10 Hz nV/Hz f = 1 kHz fA/Hz f = 1 kHz MCP6143 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = 25C, VCM = VDD/2, VOUT VDD/2, RL = 1 M to VDD/2, and CL = 60 pF. Parameters CS Low Specifications CS Logic Threshold, Low CS Input Current, Low CS High Specifications CS Logic Threshold, High CS Input Current, High CS Input High, GND Current Amplifier Output Leakage, CS High Dynamic Specifications CS Low to Amplifier Output Turn-on Time CS High to Amplifier Output High-Z Hysteresis Sym. Min. Typ. Max. Units Conditions VIL ICSL VSS -- -- 5 VSS+0.3 -- V pA CS = VSS VIH ICSH ISS IOLEAK VDD-0.3 -- -- -- -- 5 -20 20 VDD -- -- -- V pA pA pA CS = VDD CS = VDD CS = VDD tON tOFF VHYST -- -- -- 2 10 0.6 50 -- -- ms G = +1V/V, CS = 0.3V to VOUT = 0.9VDD/2 G = +1V/V, CS = VDD-0.3V to VOUT = 0.1VDD/2 VDD = 5.0V s V CS VIL tON VIH tOFF High-Z VOUT High-Z -0.6 A (typ.) ISS -20 pA (typ.) ICS 5 pA (typ.) -20 pA (typ.) 5 pA (typ.) FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6143 only). (c) 2005 Microchip Technology Inc. DS21668B-page 3 MCP6141/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SOT-23 Thermal Resistance, 6L-SOT-23 Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note 1: JA JA JA JA JA JA JA JA -- -- -- -- -- -- -- -- 256 230 85 163 206 70 120 100 -- -- -- -- -- -- -- -- C/W C/W C/W C/W C/W C/W C/W C/W TA TA TA TA -40 -40 -40 -65 -- -- -- -- +85 +125 +125 +150 C C C C Industrial Temperature parts Extended Temperature parts (Note 1) Sym. Min. Typ. Max. Units Conditions The MCP6141/2/3/4 family of Industrial Temperature op amps operates over this extended range, but with reduced performance. In any case, the internal Junction Temperature (TJ) should not exceed the Absolute Maximum specification of +150C. DS21668B-page 4 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = 25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 M to VDD/2, VOUT VDD/2, and CL = 60 pF. 14% Percentage of Occurrences 12% 10% 8% 6% 4% 2% 0% -3 -2 -1 0 1 2 3 Input Offset Voltage (mV) Percentage of Occurrences 1200 Samples VDD = 1.4V 16% 14% 12% 10% 8% 6% 4% 2% 0% -3 -2 -1 0 1 2 3 Input Offset Voltage (mV) 1200 Samples VDD = 5.5V FIGURE 2-1: VDD = 1.4V. 18% Percentage of Occurrences 16% 14% 12% 10% 8% 6% 4% 2% 0% -10 -8 -6 Input Offset Voltage at FIGURE 2-4: VDD = 5.5V. 30% Percentage of Occurrences 25% 20% 15% 10% 5% 0% Input Offset Voltage at 235 Samples VDD = 1.4V TA = -40C to +125C 235 Samples VDD = 5.5V TA = -40C to +125C -4 -2 0 2 4 6 8 10 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage Drift (V/C) Input Offset Voltage Drift (V/C) FIGURE 2-2: VDD = 1.4V. 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 VDD = 1.4V Input Offset Voltage Drift at FIGURE 2-5: VDD = 5.5V. 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 VDD = 5.5V Input Offset Voltage Drift at Input Offset Voltage (V) TA = +125C TA = +85C Input Offset Voltage (V) TA = +125C TA = +85C TA = +25C TA = -40C -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 TA = +25C TA = -40C -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.4V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. (c) 2005 Microchip Technology Inc. DS21668B-page 5 6.0 MCP6141/2/3/4 Note: Unless otherwise indicated, TA = 25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 M to VDD/2, VOUT VDD/2, and CL = 60 pF. 500 Input Offset Voltage (V) Input, Output Voltages (V) RL = 50 k 450 400 350 VDD = 5.5V 300 250 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) VDD = 1.4V 6 5 4 3 2 1 0 -1 0 5 10 15 Time (5 ms/div) 20 25 VOUT VIN VDD = 5.0V G = +11 V/V FIGURE 2-7: Output Voltage. 1,000 Input Offset Voltage vs. FIGURE 2-10: The MCP6141/2/3/4 family shows no phase reversal. 300 250 200 150 100 50 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 125 Input Noise Voltage Density (nV/ Hz) Input Noise Voltage Density (nV/ Hz) f = 1 kHz VDD = 5.0V 100 0.1 1 10 Frequency (Hz) 100 1000 Common Mode Input Voltage (V) FIGURE 2-8: vs. Frequency. 90 80 CMRR, PSRR (dB) 70 60 Input Noise Voltage Density FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. 100 PSRR, CMRR (dB) 95 PSRR (VCM = VSS) 90 85 80 75 70 CMRR (VDD = 5.0V, VCM = -0.3V to +5.3V) PSRR- PSRR+ CMRR 50 40 30 20 1 1 10 10 100 1k 100 1,000 Frequency (Hz) 10k 10,000 Referred to Input -50 -25 0 25 50 75 100 Ambient Temperature (C) FIGURE 2-9: Frequency. CMRR, PSRR vs. FIGURE 2-12: Temperature. CMRR, PSRR vs. Ambient DS21668B-page 6 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 Note: Unless otherwise indicated, TA = 25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 M to VDD/2, VOUT VDD/2, and CL = 60 pF. Input Bias and Offset Currents (pA) 10000 10k 1k 1000 100 100 10 10 11 0.1 0.1 45 55 65 75 85 95 105 115 125 Ambient Temperature (C) | IOS | VDD = 5.5V VCM = VDD 10k 10000 Input Bias, Offset Currents (pA) 1k 1000 100 10 TA = +85C 1 1 0.1 0.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) TA = +125C IB VDD = 5.5V IB | IOS | FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. 120 Open-Loop Gain (dB) 100 80 60 40 20 0 -20 Gain Phase 0 Open-Loop Phase () -30 -60 -90 -120 -150 -180 -210 FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. 130 DC Open-Loop Gain (dB) 120 110 100 90 80 70 60 100 1.E+02 VOUT = 0.1V to VDD - 0.1V 1k 10k 1.E+03 1.E+04 Load Resistance () 100k 1.E+05 VDD = 1.4V VDD = 5.5V -40 -240 10m 100m 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 10 100 1k 10k 100k 1.E- 1.E- 1 02 01 00 Frequency (Hz) 01 02 03 04 05 FIGURE 2-14: Frequency. 140 Open-Loop Gain, Phase vs. FIGURE 2-17: Load Resistance. 140 DC Open-Loop Gain (dB) 130 120 110 100 90 80 70 0.00 0.05 RL = 50 k DC Open-Loop Gain vs. DC Open-Loop Gain (dB) 130 120 110 100 90 80 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) RL = 50 k VOUT = 0.1V to VDD - 0.1V VDD = 5.5V VDD = 1.4V 0.10 0.15 0.20 0.25 Output Voltage Headroom; VDD - VOH or VOL - VSS (V) FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. (c) 2005 Microchip Technology Inc. DS21668B-page 7 MCP6141/2/3/4 Note: Unless otherwise indicated, TA = 25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 M to VDD/2, VOUT VDD/2, and CL = 60 pF. 140 Channel-to-Channel Separation (dB) 130 120 110 100 90 Input Referred 80 1k 1.E+03 Frequency (Hz) Gain Bandwidth Product (kHz) 120 110 100 90 80 70 60 50 40 30 20 10 0 -0.5 0.0 0.5 1.0 1.5 120 110 100 90 80 70 60 50 40 30 20 10 0 4.0 4.5 5.0 5.5 GBWP PM (G = +10) VDD = 5.0V 2.0 2.5 3.0 3.5 10k 1.E+04 Common Mode Input Voltage FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6142 and MCP6144 only). 90 Gain Bandwidth Product (kHz) 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 Ambient Temperature (C) VDD = 1.4V GBWP 90 80 Phase Margin () 70 60 50 40 30 20 10 0 125 FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. Gain Bandwidth Product (kHz) PM (G = +10) 90 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 Ambient Temperature (C) VDD = 5.5V PM (G = +10) GBWP 90 80 60 50 40 30 20 10 0 125 Phase Margin () 70 FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature at VDD = 1.4V. 0.8 0.7 Quiescent Current (A/Amplifier) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) TA = +125C TA = +85C TA = +25C TA = -40C FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature at VDD = 5.5V. 35 30 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 Output Short Circuit Current (mA) TA = -40C TA = +25C TA = +85C TA = +125C TA = +25C TA = -40C 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (C) FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. DS21668B-page 8 (c) 2005 Microchip Technology Inc. Phase Margin () MCP6141/2/3/4 Note: Unless otherwise indicated, TA = 25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 M to VDD/2, VOUT VDD/2, and CL = 60 pF. 1000 Output Voltage Headroom, VDD - VOH or VOL - VSS (mV) Output Voltage Headroom, VDD - VOH or VOL - VSS (mV) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VDD = 5.5V RL = 50 k VOL - VSS 100 VDD - VOH 10 VOL - VSS VDD - VOH 1 0.01 0.1 1 10 -50 -25 0 25 50 75 100 125 Output Current Magnitude (mA) Ambient Temperature (C) FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. 40 FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. 10 Maximum Output Voltage Swing (V P-P) VDD = 5.5V 35 Slew Rate (V/ms) 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 Ambient Temperature (C) VDD = 1.4V Low-to-High VDD = 5.5V High-to-Low 1 VDD = 1.4V 0.1 100 1.E+02 1k 1.E+03 Frequency (Hz) 10k 1.E+04 FIGURE 2-26: Temperature. 80 Output Voltage (20 mV/div) 60 40 20 0 Slew Rate vs. Ambient FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. 80 60 Voltage (20 mV/div) 40 20 0 G = +11 V/V RL = 50 k G = -10 V/V RL = 50 k -20 -40 -60 -80 0.0 0.1 0.2 0.3 Time (100 s/div) 0.7 0.4 0.5 0.6 0.8 0.9 1.0 -20 -40 -60 -80 0.0 0.1 0.2 0.3 Time (100 s/div) 0.7 0.4 0.5 0.6 0.8 0.9 1.0 FIGURE 2-27: Pulse Response. Small Signal Non-inverting FIGURE 2-30: Response. Small Signal Inverting Pulse (c) 2005 Microchip Technology Inc. DS21668B-page 9 MCP6141/2/3/4 Note: Unless otherwise indicated, TA = 25C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 M to VDD/2, VOUT VDD/2, and CL = 60 pF. 5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 0 0 1 Time (200 s/div) 1 1 1 1 2 2 2 5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 0 0 1 Time (200 s/div) 1 1 1 1 2 2 2 VDD = 5.0V G = -10 V/V RL = 50 k VDD = 5.0V G = +11 V/V RL = 50 k FIGURE 2-31: Pulse Response. 27.5 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 0.0 0 CS Voltage (V) Large Signal Non-inverting FIGURE 2-33: Response. 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Large Signal Inverting Pulse Output Voltage (V) VDD = 5.0V G = +11 V/V VIN = +3.0V VOUT On High-Z On CS 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 10 Internal CS Switch Output (V) VOUT On CS High-to-Low VDD = 5.0V G = +11 V/V VIN = 3.0V Hysteresis CS Low-to-High VOUT High-Z 1 2 3 Time (1 ms/div) 4567 8 9 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CS Voltage (V) FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6143 only). FIGURE 2-34: Internal Chip Select (CS) Hysteresis (MCP6143 only). DS21668B-page 10 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Symbol Description MCP6143 MCP6141 (PDIP, MCP6141 (PDIP, MCP6143 MCP6142 MCP6144 SOIC, (SOT-23-5) SOIC, (SOT-23-6) MSOP) MSOP) 6 2 3 7 -- -- -- -- -- -- 4 -- -- -- -- 1, 5, 8 1 4 3 5 -- -- -- -- -- -- 2 -- -- -- -- -- 1 2 3 8 5 6 7 -- -- -- 4 -- -- -- -- -- 6 2 3 7 -- -- -- -- -- -- 4 -- -- -- 8 1, 5 1 4 3 6 -- -- -- -- -- -- 2 -- -- -- 5 -- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- -- VOUT, VOUTA Analog Output (op amp A) VIN-, VINA- VIN+, VINA+ VDD VINB+ VINB- VOUTB VOUTC VINC- VINC+ VSS VIND+ VIND- VOUTD CS NC Inverting Input (op amp A) Non-inverting Input (op amp A) Positive Power Supply Non-inverting Input (op amp B) Inverting Input (op amp B) Analog Output (op amp B) Analog Output (op amp C) Inverting Input (op amp C) Non-inverting Input (op amp C) Negative Power Supply Non-inverting Input (op amp D) Inverting Input (op amp D) Analog Output (op amp D) Chip Select No Internal Connection 3.1 Analog Outputs 3.4 Power Supply (VSS and VDD) The output pins are low-impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs are high-impedance CMOS inputs with low bias currents. The positive power supply pin (VDD) is 1.4V to 5.5V higher than the negative power supply pin (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need a local bypass capacitor (typically 0.01 F to 0.1 F) within 2 mm of the VDD pin. These can share a bulk capacitor with nearby analog parts (within 100 mm), but it is not required. 3.3 CS Digital Input This is a CMOS, Schmitt-triggered input that places the part into a low-power mode of operation. (c) 2005 Microchip Technology Inc. DS21668B-page 11 MCP6141/2/3/4 4.0 APPLICATIONS INFORMATION The MCP6141/2/3/4 family of op amps is manufactured using Microchip's state-of-the-art CMOS process These op amps are stable for gains of 10 V/V and higher. They are suitable for a wide range of general purpose, low-power applications. See Microchip's related MCP6041/2/3/4 family of op amps for applications needing unity gain stability. The second specification that describes the output swing capability of these amplifiers is the Linear Output Voltage Range. This specification defines the maximum output swing that can be achieved while the amplifier still operates in its linear region. To verify linear operation in this range, the large signal DC Open-Loop Gain (AOL) is measured at points inside the supply rails. The measurement must meet the specified AOL condition in the specification table. 4.1 Rail-to-Rail Inputs 4.3 Output Loads and Battery Life The MCP6141/2/3/4 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-10 shows the input voltage exceeding the supply voltage without any phase reversal. The input stage of the MCP6141/2/3/4 op amps uses two differential CMOS input stages in parallel. One operates at low Common mode input voltage (VCM), while the other operates at high VCM. With this topology, the device operates with VCM tp to 0.3V above VDD and 0.3V below VSS. The input offset voltage (VOS) is measured at VCM = VSS - 0.3V and VDD + 0.3V to ensure proper operation. Input voltages that exceed the Absolute Maximum Voltage Range (VSS - 0.3V to VDD + 0.3V) can cause excessive current to flow into or out of the input pins. Current beyond 2 mA can cause reliability problems. Applications that exceed this rating must be externally limited with a resistor, as shown in Figure 4-1. RIN VA RIN VB ( Maximum expected VIN ) - V DD RIN -----------------------------------------------------------------------------2 mA V SS - ( Minimum expected V IN ) R IN -------------------------------------------------------------------------2 mA MCP614X VOUT RF The MCP6141/2/3/4 op amp family has outstanding quiescent current, which supports battery-powered applications. There is minimal quiescent current glitching when Chip Select (CS) is raised or lowered. This prevents excessive current draw, and reduced battery life, when the part is turned off or on. Heavy resistive loads at the output can cause excessive battery drain. Driving a DC voltage of 2.5V across a 100 k load resistor will cause the supply current to increase by 25 A, depleting the battery 43 times as fast as IQ (0.6 A, typ.) alone. High frequency signals (fast edge rate) across capacitive loads will also significantly increase supply current. For instance, a 0.1 F capacitor at the output presents an AC impedance of 15.9 k (1/2fC) to a 100 Hz sinewave. It can be shown that the average power drawn from the battery by a 5.0 Vp-p sinewave (1.77 Vrms), under these conditions, is EQUATION 4-1: PSupply = (VDD - VSS) (IQ + VL(p-p) f CL ) = (5V)(0.6 A + 5.0Vp-p * 100Hz * 0.1F) = 3.0 W + 50 W This will drain the battery 18 times as fast as IQ alone. 4.4 4.4.1 Stability NOISE GAIN FIGURE 4-1: Resistor (RIN). Input Current-Limiting 4.2 Rail-to-Rail Output The MCP6141/2/3/4 op amp family is designed to give high bandwidth and slew rate for circuits with high noise gain (GN) or signal gain. Low gain applications should be realized using the MCP6041/2/3/4 op amp family; this simplifies design and implementation issues. Noise gain is defined to be the gain from a voltage source at the non-inverting input to the output when all other voltage sources are zeroed (shorted out). Noise gain is independent of signal gain and depends only on components in the feedback loop. The amplifier circuits in Figure 4-2 and Figure 4-3 have their noise gain calculated as follows: There are two specifications that describe the output swing capability of the MCP6141/2/3/4 family of op amps. The first specification (Maximum Output Voltage Swing) defines the absolute maximum swing that can be achieved under the specified load condition. Thus, the output voltage swings to within 10 mV of either supply rail with a 50 k load to VDD/2. Figure 2-10 shows how the output voltage is limited when the input goes beyond the linear region of operation. DS21668B-page 12 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 EQUATION 4-2: RF G N = 1 + ------ 10 V/V RG In order for the amplifiers to be stable, the noise gain should meet the specified minimum noise gain. Note that a noise gain of GN = +10 V/V corresponds to a non-inverting signal gain of G = +10 V/V, or to an inverting signal gain of G = -9 V/V. RIN VIN MCP614X RG RF VOUT 4.4.2 CAPACITIVE LOADS Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 60 pF when G = +10), a small series resistor at the output (RISO in Figure 4-5) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. RG RF RISO MCP614X VOUT CL VB FIGURE 4-2: Noise Gain for Non-inverting Gain Configuration. RG VIN RIN MCP614X RF VOUT VA FIGURE 4-5: Output Resistor, RISO stabilizes large capacitive loads. Figure 4-6 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -9 V/V gives GN = +10 V/V). 100k 100,000 Recommended RISO ( : ) FIGURE 4-3: Noise Gain for Inverting Gain Configuration. Figure 4-4 shows a unity gain buffer and Miller integrator that are unstable when used with the MCP6141/2/3/4 family. Note that the capacitor makes the integrator circuit reach unity gain at high frequencies, which makes these op amps unstable. Unity Gain Buffer 10k 10,000 GN = +10 GN = +20 +50 GN t 1k 1,000 100p 1n 1p 10p 1.E+00 1.E+01 1.E+02 1.E+03 Normalized Load Capacitance; C L/GN (F) MCP614X VIN Miller Integrator R VIN MCP614X C VOUT VOUT FIGURE 4-6: Recommended RISO Values for Capacitive Loads. After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6141/2/3/4 SPICE macro model are helpful. FIGURE 4-4: Typical Unstable Circuits for the MCP6141/2/3/4 Family. (c) 2005 Microchip Technology Inc. DS21668B-page 13 MCP6141/2/3/4 4.5 MCP6143 Chip Select (CS) 4.8 PCB Surface Leakage The MCP6143 is a single op amp with Chip Select (CS). When CS is pulled high, the supply current drops to 50 nA (typ.) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier may not operate properly. Figure 1-1 shows the output voltage and supply current response to a CS pulse. In applications where low input bias current is critical, printed circuit board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6141/2/3/4 family's bias current at 25C (1 pA, typ.). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-8. Guard Ring VIN- VIN+ 4.6 Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high frequency performance. It can use a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor is not required for most applications and can be shared with other nearby analog parts. 4.7 Unused Op Amps FIGURE 4-8: for Inverting Gain. 1. An unused op amp in a quad package (MCP6144) should be configured as shown in Figure 4-7. These circuits prevent the output from toggling and causing crosstalk. Circuits A and B are set near the minimum noise gain. Circuit A can use any reference voltage between the supplies, provides a buffered DC voltage, and minimizes the supply current draw of the unused op amp. Circuit B may draw a little more supply current for the unused op amp. Circuit C uses the minimum number of components and operates as a comparator; it may draw more current than either Circuit A or B. 1/4 MCP6144 (A) VDD R VDD 1/4 MCP6144 (B) VDD Example Guard Ring Layout 2. R R R 15R 10R Non-inverting Gain and Unity Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the Common mode input voltage. Inverting Gain and Trans-impedance Gain (convert current to voltage, such as photo detectors) amplifiers: a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. 1/4 MCP6144 (C) VDD FIGURE 4-7: Unused Op Amps. DS21668B-page 14 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 4.9 4.9.1 Application Circuits BATTERY CURRENT SENSING 4.9.2 INVERTING SUMMING AMPLIFIER The MCP6141/2/3/4 op amps' Common Mode Input Range, which goes 0.3V beyond both supply rails, supports their use in high side and low side battery current sensing applications. The very low quiescent current (0.6 A, typ.) help prolong battery life, and the rail-to-rail output supports detection low currents. Figure 4-9 shows a high side battery current sensor circuit. The 1 k resistor is sized to minimize power losses. The battery current (IDD) through the 1 k resistor causes its top terminal to be more negative than the bottom terminal. This keeps the Common mode input voltage of the op amp at VDD, which is within its allowed range. When no current is flowing, the output will be at its Maximum Output Voltage Swing (VOH), which is virtually at VDD. . The MCP6141/2/3/4 op amp is well suited for the inverting summing amplifier shown in Figure 4-10 when the resistors at the input (R1, R2, and R3) make the noise gain at least 10 V/V. The output voltage (VOUT) is a weighted sum of the inputs (V1, V2, and V3), and is shifted by the VREF input. The necessary calculations follow in Equation 4-3. . R1 V1 R2 V2 R3 V3 MCP614X VREF RF VOUT VDD VDD VOUT MCP6141 VSS 1 M FIGURE 4-10: EQUATION 4-3: Noise Gain: Summing Amplifier. 1 k IDD 100 k 1.4V to 5.5V VSS 1- 1- 1GN = 1 + R F ----- + ----- + ----- 10 V/V R R R 1 2 3 Signal Gains: G1 = - R F R 1 G2 = - R F R 2 G3 = - R F R 3 Output Signal: VOUT = V1 G 1 + V2 G 2 + V 3 G 3 + V REF G N FIGURE 4-9: Sensor. High Side Battery Current (c) 2005 Microchip Technology Inc. DS21668B-page 15 MCP6141/2/3/4 5.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6141/2/3/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6141/2/3/4 op amps is available on our web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation at room temperature. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab(R) Software The FilterLab software is an innovative tool that simplifies analog active filter (using op amps) design. It is available free of charge from our web site at www.microchip.com. The FilterLab software tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. DS21668B-page 16 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 6.0 6.1 PACKAGING INFORMATION Package Marking Information 5-Lead SOT-23 (MCP6141) Example: Device E-Temp Code ASNN XXNN MCP6141 Note: Applies to 5-Lead SOT-23 AS25 6-Lead SOT-23 (MCP6143) Example: Device E-Temp Code AWNN XXNN MCP6143 Note: Applies to 6-Lead SOT-23 AW25 8-Lead MSOP XXXXXX YWWNNN Example: 6143I 536256 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2005 Microchip Technology Inc. DS21668B-page 17 MCP6141/2/3/4 Package Marking Information (Continued) 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP6141 I/P256 0223 MCP6141 E/P e3 256 0536 OR 8-Lead SOIC (150 mil) Example: XXXXXXXX XXXXYYWW NNN MCP6142 I/SN0223 256 OR MCP6142E SN e3 0536 256 14-Lead PDIP (300 mil) (MCP6144) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP6144-I/P 0434256 OR MCP6144 I/P e3 0536256 DS21668B-page 18 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 Package Marking Information (Continued) 14-Lead SOIC (150 mil) (MCP6144) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP6144ISL 0434256 OR MCP6144 e3 I/SL^^ 0536256 14-Lead TSSOP (MCP6144) Example: XXXXXXXX YYWW NNN 6144ST 0534 256 OR 6144EST 0534 256 (c) 2005 Microchip Technology Inc. DS21668B-page 19 MCP6141/2/3/4 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) E E1 p B p1 D n 1 c A A2 Units Dimension Limits Number of Pins Pitch Outside lead pitch (basic) Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n p p1 A A2 A1 E E1 D L f c B a b L A1 INCHES* MIN NOM 5 .038 .075 .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 0.35 0.90 0.90 0.00 2.60 1.50 2.80 0.35 MAX MIN MILLIMETERS NOM 5 0.95 1.90 1.18 1.10 0.08 2.80 1.63 2.95 0.45 0 0.09 0 0 0.15 0.43 5 5 5 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 MAX * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Revised 09-12-05 Drawing No. C04-091 DS21668B-page 20 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 6-Lead Plastic Small Outline Transistor (CH) (SOT-23) E E1 B p1 D n 1 c A A2 L A1 Units Dimension Limits Number of Pins Pitch Outside lead pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n p p1 A A2 A1 E E1 D L c B .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 MIN INCHES* NOM 6 .038 BSC .075 BSC .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 0.35 0 0 0.90 0.90 0.00 2.60 1.50 2.80 0.35 0 0.09 MAX MIN MILLIMETERS NOM 6 0.95 BSC 1.90 BSC 1.18 1.10 0.08 2.80 1.63 2.95 0.45 5 0.15 0.43 5 5 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 MAX * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M JEITA (formerly EIAJ) equivalent: SC-74A Revised 09-12-05 Drawing No. C04-120 (c) 2005 Microchip Technology Inc. DS21668B-page 21 MCP6141/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 n 1 B c A A2 F Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint (Reference) Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n p A A2 A1 E E1 D L F c B .016 .030 .000 MIN L A1 INCHES NOM 8 MAX MIN MILLIMETERS* NOM 8 0.65 BSC .043 .037 .006 0.75 0.00 4.90 BSC 3.00 BSC 3.00 BSC .031 8 .009 .016 15 15 0.40 0 0.08 0.22 5 5 0.60 0.95 REF 8 0.23 0.40 15 15 0.80 0.85 1.10 0.95 0.15 MAX .026 BSC .033 .193 BSC .118 BSC .118 BSC .024 .037 REF 0 .003 .009 5 5 .006 .012 - * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-187 Drawing No. C04-111 Revised 07-21-05 DS21668B-page 22 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 8-Lead Plastic Dual In-line (P) - 300 mil Body (PDIP) E1 D 2 n 1 E A A2 c L A1 eB B1 p B MAX Number of Pins Pitch Top to Seating Plane A .140 .170 4.32 Molded Package Thickness A2 .115 .145 3.68 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 8.26 Molded Package Width E1 .240 .250 .260 6.60 Overall Length D .360 .373 .385 9.78 Tip to Seating Plane L .125 .130 .135 3.43 c Lead Thickness .008 .012 .015 0.38 Upper Lead Width B1 .045 .058 .070 1.78 Lower Lead Width B .014 .018 .022 0.56 Overall Row Spacing eB .310 .370 .430 10.92 Mold Draft Angle Top 5 10 15 15 Mold Draft Angle Bottom 5 10 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 Units Dimension Limits n p MIN INCHES* NOM 8 .100 .155 .130 MAX MIN MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 (c) 2005 Microchip Technology Inc. DS21668B-page 23 MCP6141/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E1 D 2 n 1 E A A2 c L A1 eB B1 p B MAX Number of Pins Pitch Top to Seating Plane A .140 .170 4.32 Molded Package Thickness A2 .115 .145 3.68 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 8.26 Molded Package Width E1 .240 .250 .260 6.60 Overall Length D .360 .373 .385 9.78 Tip to Seating Plane L .125 .130 .135 3.43 c Lead Thickness .008 .012 .015 0.38 Upper Lead Width .045 .058 .070 1.78 B1 Lower Lead Width B .014 .018 .022 0.56 eB Overall Row Spacing .310 .370 .430 10.92 Mold Draft Angle Top 5 10 15 15 Mold Draft Angle Bottom 5 10 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 Units Dimension Limits n p MIN INCHES* NOM 8 .100 .155 .130 MAX MIN MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 DS21668B-page 24 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 14-Lead Plastic Dual In-line (P) - 300 mil Body (PDIP) E1 D 2 n 1 E A A2 c eB A1 B1 B p L MAX Number of Pins Pitch Top to Seating Plane A .140 .170 4.32 Molded Package Thickness A2 .115 .145 3.68 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 8.26 Molded Package Width .240 .250 .260 6.60 E1 Overall Length D .740 .750 .760 19.30 Tip to Seating Plane L .125 .130 .135 3.43 c Lead Thickness .008 .012 .015 0.38 Upper Lead Width B1 .045 .058 .070 1.78 Lower Lead Width B .014 .018 .022 0.56 Overall Row Spacing eB .310 .370 .430 10.92 Mold Draft Angle Top 5 10 15 15 5 10 15 15 Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MIN MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 (c) 2005 Microchip Technology Inc. DS21668B-page 25 MCP6141/2/3/4 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil Body (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L A1 MAX Number of Pins Pitch Overall Height A .053 .069 1.75 Molded Package Thickness A2 .052 .061 1.55 Standoff A1 .004 .010 0.25 Overall Width E .228 .244 6.20 Molded Package Width E1 .150 .157 3.99 Overall Length D .337 .347 8.81 Chamfer Distance h .010 .020 0.51 Foot Length L .016 .050 1.27 Foot Angle 0 8 8 c Lead Thickness .008 .010 0.25 Lead Width B .014 .020 0.51 Mold Draft Angle Top 0 15 15 Mold Draft Angle Bottom 0 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 Units Dimension Limits n p MIN INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX MIN MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 DS21668B-page 26 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body (TSSOP) E E1 p D 2 n B 1 A c L Units Dimension Limits MIN n p A A2 A1 E E1 D L c B .039 .033 .002 .246 .169 .193 .020 0 .004 .007 INCHES NOM 14 .026 BSC .041 .035 .004 .251 .173 .197 .024 4 .006 .010 12 REF 12 REF A1 MILLIMETERS* MAX MIN NOM 14 0.65 BSC .043 .037 .006 .256 .177 .201 .028 8 .008 .012 1.00 0.85 0.05 6.25 4.30 4.90 0.50 0 0.09 0.19 1.05 0.90 0.10 6.38 4.40 5.00 0.60 4 0.15 0.25 12 REF 12 REF A2 MAX Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom 1.10 0.95 0.15 6.50 4.50 5.10 0.70 8 0.20 0.30 * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-153 AB-1 Drawing No. C04-087 Revised: 08-17-05 (c) 2005 Microchip Technology Inc. DS21668B-page 27 MCP6141/2/3/4 NOTES: DS21668B-page 28 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 APPENDIX A: REVISION HISTORY Revision B (November 2005) The following is the list of modifications: 1. Added the following: a) SOT-23-5 package for the MCP6141 single op amps. b) SOT-23-6 package for the MCP6143 single op amps with Chip Select. c) Extended Temperature (-40C to +125C) op amps. Updated specifications in Section 1.0 "Electrical Characteristics" for E-temp parts. Corrected and updated plots in Section 2.0 "Typical Performance Curves". Added Section 3.0 "Pin Descriptions". Updated Section 4.0 "Applications Information" and added section on unused op amps. Updated Section 5.0 "Design Tools" to include FilterLab. Added SOT-23-5 and SOT-23-6 packages and corrected package marking information in Section 6.0 "Packaging Information". Added Appendix A: "REVISION HISTORY". 2. 3. 4. 5. 6. 7. 8. Revision A (September 2002) * Original Release of this Document. (c) 2005 Microchip Technology Inc. DS21668B-page 29 MCP6141/2/3/4 NOTES: DS21668B-page 30 (c) 2005 Microchip Technology Inc. MCP6141/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X Temperature Range MCP6141: MCP6141T: MCP6142: MCP6142T: MCP6143: MCP6143T: MCP6144: MCP6144T: / XX Package Examples: a) b) MCP6141-I/P: MCP6141T-E/OT: Industrial Temp., 8LD PDIP package. Tape and Reel, Extended Temp., 5LD SOT-23 package. Device: Single Op Amp Single Op Amp (Tape and Reel for SOT-23, SOIC, MSOP) Dual Op Amp Dual Op Amp (Tape and Reel for SOIC and MSOP) Single Op Amp w/ CS Single Op Amp w/ CS (Tape and Reel for SOT-23, SOIC, MSOP) Quad Op Amp Quad Op Amp (Tape and Reel for SOIC and TSSOP) a) b) MCP6142-I/SN: MCP6142T-E/MS: Industrial Temp., 8LD SOIC package. Tape and Reel, Extended Temp., 8LD MSOP package. a) b) MCP6143-I/P: MCP6143T-E/CH: Temperature Range: I E = -40C to +85C (Industrial) = -40C to +125C (Extended) a) MCP6144-I/SL: MCP6144T-E/ST: Industrial Temp., 8LD PDIP package. Tape and Reel, Extended Temp., 6LD SOT-23 package. Package: CH MS OT P SL SN ST = Plastic Small Outline Transistor (SOT-23), 6-lead (Tape and Reel - MCP6143 only) = Plastic Micro Small Outline (MSOP), 8-lead = Plastic Small Outline Transistor (SOT-23), 5-lead (Tape and Reel - MCP6141 only) = Plastic DIP (300 mil Body), 8-lead, 14-lead = Plastic SOIC (150 mil Body), 14-lead = Plastic SOIC (150 mil Body), 8-lead = Plastic TSSOP (4.4 mm Body), 14-lead b) Industrial Temp., 14LD PDIP package. Tape and Reel, Extended Temp., 14LD TSSOP package. (c) 2005 Microchip Technology Inc. DS21668B-page 31 MCP6141/2/3/4 NOTES: DS21668B-page 32 (c) 2005 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2005 Microchip Technology Inc. DS21668B-page 33 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 10/31/05 DS21668B-page 34 (c) 2005 Microchip Technology Inc. |
Price & Availability of MCP6142-ISN
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |